A voltage reference circuit is an electronic device (circuit or component) that produces a fixed (constant) voltage irrespective of the loading on the device, process, power supply variation and temperature. A voltage reference circuit is one of important analog blocks in integrated circuits.
One common voltage reference circuit used in integrated circuits is the bandgap voltage reference circuit. A bandgap-based reference circuit uses analog circuits to add a multiple of the voltage difference between two bipolar junctions biased at different current densities to the voltage developed across a diode. The diode voltage has a negative temperature coefficient (i.e. it decreases with increasing temperature), and the junction voltage difference has a positive temperature coefficient. When added in the proportion required to make these coefficients cancel out, the resultant constant value is a voltage equal to the bandgap voltage of the semiconductor. However, the bandgap design requires relatively large area and power.
Another voltage reference circuit design is a constant transconductance (Gm) design.
FIG. 1A is a schematic diagram of a conventional constant Gm voltage reference circuit without temperature compensation. Two PMOS transistors 102 and 104 that are connected to VDD share the gate connections. NMOS transistors 106 and 108 are connected to PMOS transistors 102 and 104 and share the gate connections to the output voltage VREF, while the gate and drain of PMOS 104 are connected together and the gate and drain of NMOS 106 are connected together. The NMOS channel size ratio of 106 and 108 are W/L:K(W/L)=1:K, where W/L is the width over length of the channel of the NMOS transistors. The source of NMOS 106 is connected to ground (VSS) and the source of NMOS 108 is connected to ground (VSS) through resistor Rs 110. Constant Gm design requires relatively small area and power, but suffers from a strong temperature dependence.
With VTH as the threshold voltage of NMOS 108, the current and voltage of the voltage reference circuit shown in FIG. 1A are given by the following equations:
                              I          ⁢                                          ⁢          ref                =                              2                                          μ                N                            ⁢                                                                    C                    OX                                    ⁡                                      (                                          W                      L                                        )                                                  N                            *                              Rs                2                                              ⁢                                    (                              1                -                                  1                                      K                                                              )                        2                                              (                  Eq          .                                          ⁢          1                )                                          VREF          =                                    V              TH                        +                                                            2                  ⁢                                      I                    ref                                                                                        μ                    N                                    ⁢                                      C                    ox                                    ⁢                                                            K                      ⁡                                              (                                                  W                          L                                                )                                                              N                                                                        +                                          I                ref                            ⁢                              R                S                                                    ,                            (                  Eq          .                                          ⁢          2                )            where μN is the mobility of the NMOS, Cox is the gate oxide capacitance, W/L is the width over length of the channel of the NMOS.
With increasing temperature, the mobility μN decreases, therefore results in higher Iref in Eq. 1. On the other hand, with increasing temperature, the threshold voltage VTH decreases, resulting in lower VREF in Eq. 2. Therefore VREF shows strong dependency on temperature. For example, compared to an exemplary bandgap design voltage reference circuit with a layout area of 77×53 μm2 and 180 μA current requirement that showed about 3 mV variation over −40° C.-125° C., an exemplary constant Gm design voltage reference circuit with a layout area of 24×7.3 μm2 and 10 μA current requirement showed a temperature variation of 18 mV over the same temperature range, as shown in FIG. 1B (a temperature vs. voltage output plot for an exemplary voltage reference circuit shown in FIG. 1A).
Accordingly, new temperature compensation schemes are desired for voltage reference with constant Gm design.